Memory devices are prone to a phenomenon known as leakage power. Leakage power is typically dissipated by logic in the periphery and core memory arrays whenever the memory is powered on. As technology shrinks below sub-nanometer geometries, the leakage power dissipation in a memory device increases. This leakage power is becoming a more significant component of the total power dissipation in the memory.
One way to reduce leakage power is to reduce the power supply voltage for the memory device. However, the voltage level of a bit cell in the memory needs to be maintained at a minimum voltage specification for retention, while periphery sections of the memory device can operate below the specified voltage. As a result, dual rail power supplies have been developed where the periphery and core of a memory operate with different power supplies at different voltages, in an effort to reduce leakage power. Memories with dual rail power supplies use level shifters to isolate a high-voltage domain (e.g., VDDA) for one group of circuits from a low-voltage domain (e.g., VDD) for another group of circuits and convert signal voltages passing through the level shifters to the appropriate domain.